{"id":233947,"date":"2026-06-25T10:15:31","date_gmt":"2026-06-25T10:15:31","guid":{"rendered":"https:\/\/teknomers.com\/en\/the-first-sub-1nm-chip-has-arrived-manufactured-by-ibm-and-its-spectacular\/"},"modified":"2026-06-25T10:15:34","modified_gmt":"2026-06-25T10:15:34","slug":"the-first-sub-1nm-chip-has-arrived-manufactured-by-ibm-and-its-spectacular","status":"publish","type":"post","link":"https:\/\/teknomers.com\/en\/the-first-sub-1nm-chip-has-arrived-manufactured-by-ibm-and-its-spectacular\/","title":{"rendered":"The First Sub-1nm Chip Has Arrived: Manufactured by IBM and It’s Spectacular"},"content":{"rendered":"\n
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It has been a long time since we witnessed a milestone like this. Innovations in the field of semiconductor manufacturing occur constantly, but what IBM has just announced is a monumental achievement: it has managed to produce the world’s first chip with subnanometer technology<\/strong>. This simply means that it has been manufactured on a 0.7 nm (or 7 angstroms) node, which has allowed this company’s engineers to pack almost 100 billion transistors into a surface the size of a fingernail.<\/p>\n

Crossing the nanometer barrier is not just a matter of numbers. For decades, the integrated circuit industry has evolved under the logic of Moore’s Law. The problem is that this principle has been losing force as transistors approach the dimensions of atoms themselves. Quantum physics is relentless: each further reduction in size presents an almost unsolvable problem. Reaching 0.7 nm signifies that IBM has found a way out of that alley. Crucially, it’s not through conventional miniaturization methods, but through completely reinventing how transistors are designed and built.<\/p>\n

Performance and Efficiency Breakthroughs<\/h2>\n

This new chip offers up to 50% more performance compared to previous technologies. Furthermore, it boasts a 70% improvement in energy efficiency compared to IBM’s own 2nm integrated circuits. These metrics illustrate the flexibility that designers can leverage for various applications, ranging from generative artificial intelligence (AI) to next-gen devices. This degree of adaptability often determines whether a chip is merely viable or truly disruptive in the marketplace.<\/p>\n

Unveiling the Nanostack Technology<\/h2>\n

The cornerstone of IBM’s 0.7nm integrated circuit innovation is the technology called nanostack<\/em>. This represents the industry’s first three-dimensional architecture based on stacked nanosheets, developed entirely by IBM. To grasp its significance, we need to revisit the previous generation of technological leap: nanosheets. Instead of a single vertical fin as seen in FinFET transistors, nanosheets consist of multiple horizontal sheets of silicon stacked and wrapped around the control gate, significantly enhancing electrical performance in a more compact space.<\/p>\n

Nanostack<\/em> takes this a step further by staggering entire transistors in three dimensions. This 3D sequential integration optimizes space utilization, allowing for more logic in less surface area<\/strong>. Unlike simple miniaturization, this architecture enables various materials to be combined within each stacked layer, which allows for individualized performance and energy efficiency optimization for each transistor.<\/p>\n

Tailoring Performance<\/h3>\n

Importantly, not all transistors on a chip need to behave the same. Some may prioritize speed while others focus on energy savings. Nanostack<\/em> also enables a fine-tuning of these parameters on a layer-by-layer basis, offering a level of granularity that planar architectures and even conventional nanosheets cannot match. <\/p>\n

Looking Ahead: Commercial Viability<\/h2>\n

IBM has recently presented promising results at the VLSI 2026 conference, demonstrating a 40% improvement in SRAM scaling thanks to this architecture. This breakthrough is particularly crucial for manufacturing semiconductors that can handle the demanding bandwidth requirements of advanced AI workloads. The architecture’s experimental validation rests on three pillars: the ultra-thin dielectric link in CMOS integration, demonstrated dual-channel engineering capability, and the functional operation of a CMOS inverter with expected switching performance<\/strong>.<\/p>\n

The advent of a functional CMOS inverter confirms that nanostack<\/em> is not simply a laboratory concept; it is indeed a technology that can be physically constructed and integrated into real computing systems.<\/p>\n

IBM, along with its partners\u2014Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions\u2014has been diligently working on ASML’s High NA extreme ultraviolet lithography manufacturing tools and processes at its facility in Albany, New York. However, the journey from laboratory to manufacturers is lengthy; IBM estimates a production timeline of three to five years for the first commercial rollout of the nanostack<\/em> technology within a sub-nanometer framework. They foresee at least another decade of scaling ahead.<\/p>\n

Moreover, IBM has announced the establishment of Anderon, an independent quantum chip manufacturing entity that will leverage its expertise in quantum computing and semiconductor technologies to produce quantum wafers at an industrial scale.<\/p>\n

In conclusion, with the advent of the 7-angstrom node, IBM has not only proven that subnanometer scaling is physically attainable<\/strong>, but it has also positioned itself as a leader and reference point in an industry that has long sought alternatives beyond the limitations of traditional silicon-based technologies.<\/p>\n<\/div>\n


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General News – 2<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

It has been a long time since we witnessed a milestone like this. Innovations in the field of semiconductor manufacturing occur constantly, but what IBM has just announced is a monumental achievement: it has managed to produce the world’s first chip with subnanometer technology. This simply means that it has been manufactured on a 0.7 […]<\/p>\n","protected":false},"author":1,"featured_media":233948,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[36399],"tags":[757,10792,48915,37481,8043,54439],"class_list":["post-233947","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technology","tag-arrived","tag-chip","tag-ibm","tag-manufactured","tag-spectacular","tag-sub1nm"],"_links":{"self":[{"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/posts\/233947","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/comments?post=233947"}],"version-history":[{"count":1,"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/posts\/233947\/revisions"}],"predecessor-version":[{"id":233949,"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/posts\/233947\/revisions\/233949"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/media\/233948"}],"wp:attachment":[{"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/media?parent=233947"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/categories?post=233947"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/teknomers.com\/en\/wp-json\/wp\/v2\/tags?post=233947"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}