Nvidia is preparing to open the door to \u00a0photonic silicon\u00a0. Just a few hours ago, it has started in Palo Alto, California (USA), the \u00a0Specialized Conference in Semiconductor Engineering and High Performance Computing\u00a0 known as ‘Hot Chips’. The company, led by Jensen Huang, has seized this opportunity to announce that in 2026, its latest generation artificial intelligence (AI) platforms will utilize \u00a0photonic interconnections\u00a0 to achieve higher transfer speeds between GPU clusters.<\/p>\n
<\/p>\n
Most designers and manufacturers of integrated circuits are currently focused on developing \u00a0silicon photonics\u00a0. Douglas Yu, a TSMC executive responsible for systems integration, articulated its disruptive potential in September 2023: “If we manage to implement a good system of integration of silicon photonics, we will trigger a new paradigm. We will probably place ourselves at the \u00a0beginning of a new era\u00a0.”<\/p>\n
<\/p>\n
Before delving deeper, it\u2019s essential to understand what we mean by \u00a0photonic silicon\u00a0. This emerging discipline seeks to harness the properties of silicon to optimize the transformation of \u00a0electrical signals\u00a0 into \u00a0light pulses\u00a0. The primary application of this technology lies in establishing high-performance links that can enhance communications between multiple chips and facilitate the transfer of information between various machines.<\/p>\n
<\/p>\n
Advanced \u00a0packaging technologies\u00a0 employed by leading semiconductor manufacturers such as TSMC, Intel, and Samsung can significantly benefit from efficient communication mechanisms between high-performance chips. Moreover, large \u00a0data centers\u00a0, where a multitude of machines must be interconnected, stand to gain immensely from this innovation. However, the most promising application of photonic silicon occurs within the realm of \u00a0artificial intelligence\u00a0.<\/p>\n
<\/p>\n
CPO technology reduces energy consumption to just 9 watts per port<\/p>\n<\/p><\/div>\n<\/div>\n
This is precisely Nvidia\u2019s ambition. In these clusters, thousands of GPUs must work in unison; thus, establishing high-performance links is critical. Traditional solutions like copper cables or optical modules can address this issue, but they introduce substantial inefficiencies, particularly in terms of \u00a0energy loss\u00a0 and potential bottlenecks. The data transfer can consume up to \u00a030 watts per port\u00a0, resulting in excessive heat generation and increased failure rates.<\/p>\n
<\/p>\n
Furthermore, \u00a0latency\u00a0 poses a limitation to the scalability of clusters as the number of GPUs in data centers climbs. To mitigate these inefficiencies, Nvidia plans to integrate optical components that necessitate photonic interconnections directly within the encapsulated \u00a0switching chip\u00a0. This innovative technology, referred to as \u00a0CPO (Co-Packaged Optics)\u00a0, will reduce energy consumption to just \u00a09 watts per port\u00a0, minimize signal loss, and enhance data integrity. Early indications suggest this technology holds significant promise.<\/p>\n
<\/p>\n
Nvidia has confirmed that it will incorporate CPO technology into its \u00a0Quantum-X InfiniBand\u00a0 and \u00a0Spectrum-X Ethernet\u00a0 interconnection platforms by 2026. Importantly, CPO will not be an optional enhancement; it will be integrated as a fundamental requirement for the next generation of \u00a0AI data centers\u00a0, aiming to bolster the competitiveness of Nvidia\u2019s hardware platforms.<\/p>\n
<\/p>\n
Image | Nvidia<\/a><\/p>\n