## The Quest for AI Chip Efficiency
More performance? It is the first thing we usually ask of a new chip, almost without thinking about it. We have done it for years with the processors in our devices and we do it now with the chips that support much of the deployment of AI. More computing power, more speed, and greater scope for tasks previously deemed impossible are what we seek. However, this mentality is starting to hit a specific limit: energy consumption. As the landscape shifts, it becomes evident that progress can no longer be solely measured by how much a chip calculates but also by its energy efficiency.
## TSMC’s Insight on Energy Efficiency
The clearest clue comes from TSMC, the world’s largest contract chip manufacturer. Although TSMC does not sell processors under its own brand, it produces semiconductors for various industry players. According to Kevin Zhang, TSMC’s senior vice president of business development, the company is noticing a growing trend among clients who prioritize performance improvements without increasing energy consumption. This shift is evident across a spectrum of clients, from smartphone manufacturers to AI data center operators, all of whom share increasing concerns about electricity costs and energy availability.
## Innovations in Manufacturing Techniques
The focus on energy efficiency is not merely anecdotal; it’s reflected in TSMC’s technological roadmap. The company has announced plans for a future manufacturing technology known as the A14, set to launch around 2028. This process is expected to achieve a performance improvement of over 20% while simultaneously reducing energy consumption by up to 30% compared to TSMC’s N2 process. Importantly, this advancement revolves around a broader manufacturing method rather than a specific processor, setting the stage for future innovations in chip design.
### Beyond Miniaturization
For decades, miniaturizing transistors has been a primary avenue toward enhancing chip performance and efficiency. While this approach remains vital in TSMC’s roadmap, there is an increasing exploration of alternative solutions. Advanced packaging, chip stacking, and photonics are gaining traction in light of the energy demands posed by AI applications. Interestingly, TSMC has decided against adopting High-NA EUV lithography in its A13 and A12 processes scheduled for 2029, signaling a shift in priorities.
## Data Management as a Game Changer
Another significant player in this evolving landscape is Huawei, which recently introduced the Tau Scaling Law. This proposal aims to enhance performance by improving data movement within chips, thus shifting some focus from transistors to architecture and integration. Additionally, Huawei has unveiled LogicFolding, which could redefine traditional 3D stacking. This advancement necessitates new design tools for folded architectures alongside superior heat dissipation solutions across devices, from smartphones to AI data centers.
## The Path Forward
While TSMC’s viewpoints may not reflect the entire industry, their prominence lends credence to the growing emphasis on energy efficiency. Conversations with clients have led TSMC to realize that energy efficiency is taking center stage, overshadowing traditional performance metrics. This concern extends beyond AI data centers and encompasses a broader range of applications. Huawei’s architectural innovations further underline that improving chip efficiency does not rely solely on manufacturing processes but also on innovative design approaches.
In summary, as the industry progresses, there is a palpable tension: chips must become more capable, yet the justification for each leap forward becomes increasingly challenging if it leads to higher energy consumption, heat output, or production costs.